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1 of 29 070605 features unique 1-wire ? interface requires only one port pin for communication provides unique 64-bit serial number eliminates thermistors by sensing battery temperature on-chip on-board a/d converter allows monitoring of battery voltage for end-of-charge and end- of-discharge determination on-board integrated current accumulator facilitates fuel gauging elapsed time meter in binary format 40-byte nonvolatile user memory available for storage of battery-specific data reverts to low-power sleep mode on battery pack disconnect (feature disabled on DS2438AZ) operating range -40oc to +85oc applications include portable computers, portable/cellular phones, consumer electronics, and handhe ld instrumentation pin assignment pin description dq - data in/out vad - general a/d input v sens+ - battery current monitor input (+) v sens- - battery current monitor input (-) vdd - power supply (2.4v to 10.0v) gnd - ground nc - no connect description the ds2438 smart battery monitor provides several func tions that are desirable to carry in a battery pack: a means of tagging a battery pack with a uni que serial number, a dire ct-to-digital temperature sensor which eliminates the need for thermistors in the battery pack, an a/d converter which measures the battery voltage and current, an integrated curre nt accumulator which keeps a running total of all current going into and out of the battery, an el apsed time meter, and 40 by tes of nonvolatile eeprom memory for storage of important parameters such as battery chemistry, battery capacity, charging methodology and assembly date. information is sent to/from the ds2438 over a 1-wire interface, so that only one wire (and ground) needs to be connected from a central microprocessor to a ds2438. this means that battery packs need only have three out put connectors: battery power, ground, and the 1-wire interface. because each ds2438 contains a uni que silicon serial number, multiple ds2438s can exist on the same 1-wire bus. this allows multiple battery packs to be charged or used in the system simultaneously. applications for the smart battery monitor include portable computers, cellula r telephones, and handheld instrumentation battery packs in which it is critical to monitor real-time battery performance. used in conjunction with a microcontroller in the host syst em, the ds2438 provides a complete smart battery pack solution that is fully chemistry-independent. the customization for a particular battery chemistry and capacity is realized in the code programme d into the microcontroller and ds2438 eeprom, and only a software revision is necessary should a desi gner wish to change battery pack chemistry. ds2438 smart battery monito r www.maxim-ic.com gnd v sens+ v sens- v a d dq nc nc v dd 1 2 3 4 8 7 6 5 ds2438z, DS2438AZ 8-pin soic (150-mil)
ds2438 2 of 29 ordering information part marking package information ds2438z+ ds2438 8-pin soic ds2438z+t&r ds2438 ds2438z+ on tape-and-reel DS2438AZ+ ds2438a 8-pin soic DS2438AZ+t&r ds2438a DS2438AZ+ on tape-and-reel ds2438z ds2438 8-pin soic ds2438z/t&r ds2438 ds2438z on tape-and-reel DS2438AZ ds2438a 8-pin soic DS2438AZ/t&r ds2438a DS2438AZ on tape-and-reel + denotes lead-free package. detailed pin description pin symbol description 1 gnd ground 2 v sens+ battery input: connection for battery current to be monitored (see text) 3 v sens- battery input: connection for battery current to be monitored (see text) 4 v ad adc input: input for general purpose a/d 5 v dd v dd pin: input supply voltage 6, 7 nc no connect 8 dq data input/out: for 1-wire operation: open drain overview the block diagram of figure 1 shows th e seven major components of the ds2438: 1. 64-bit lasered rom 2. temperature sensor 3. battery voltage a/d 4. battery current a/d 5. current accumulators 6. elapsed time meter 7. 40-byte nonvolatile user-memory each ds2438 contains a unique 64-bit lasered rom serial number so that several battery packs can be charged/monitored by the same host system. furthe rmore, other dallas products featuring the same 1-wire bus architecture with a 64-bit rom can reside on the same bus; refer to the dallas automatic identification data book for the specifications of these products. communication to the ds2438 is via a 1-wire port. with the 1-wire port, the memory and control functions will not be available until the rom function protocol has been established. the master must first provide one of four rom func tion commands: 1) read rom, 2) ma tch rom, 3) search rom, or 4) skip rom. these commands operate on the 64-bit la sered rom portion of each device and can singulate a specific device if many are present on the 1-wire line as well as to indicate to the bus master how many and what types of devices are present. after a ro m function sequence has been successfully executed, the memory and control functions are accessible and the master may then provide any one of the six memory and control function commands.
ds2438 3 of 29 control function commands may be issued which instruct the ds2438 to perform a temperature measurement or battery voltage a/d conversion. the result of these measurements will be placed in the ds2438?s memory map, and may be read by issu ing a memory function command which reads the contents of the temperature and voltage registers. additionally, the charging/discharging battery current is measured without user intervention, and again, the la st completed result is stored in ds2438 memory space. the ds2438 uses these current measurements to update three current accumulators; the first stores net charge for fuel gauge calculations, the second accumulates the total charging current over the life of the battery, and the remaining accumulator tallies battery discharge current. the elapsed time meter data, which can be used in calculating battery self-discharge or time-related charge termination limits, also resides in the ds2438 memory map and can be ex tracted with a memory function command. the nonvolatile user memory of the ds2438 consists of 40 bytes of eeprom. these locations may be used to store any data the user wishes and are writte n to using a memory function command. all data and commands are read and written least significant bit first. parasite power the block diagram (figure 1) shows the parasite-pow ered circuitry. this circuitry ?steals? power whenever the dq pin is high. dq will provide suffi cient power as long as the specified timing and voltage requirements are met (see the section titled ?1-wire bus system?). the advantage of parasite power is that the rom may be read in absence of nor mal power, i.e., if the battery pack is completely discharged. ds2438 block diagram figure 1
ds2438 4 of 29 operation-measuring temperature the ds2438 measures temperatures through the use of an on-board temperature measurement technique. the temperature reading is provided in a 13-bit, two?s complement format, which provides 0.03125 c of resolution. table 1 describes the exact relationship of output data to m easured temperature. the data is transmitted serially over the 1-wire interface. th e ds2438 can measure temperature over the range of -55 c to +125 c in 0.03125 c increments. for fahrenheit usage, a lookup table or conversion factor must be used. note that temperature is represen ted in the ds2438 in terms of a 0.03125 c lsb, yielding the following 13-bit format. the 3 least significant bits of the temperature register will always be 0. the remaining 13 bits contain the two?s complement representation of the temperature in c, with the msb holding the sign (s) bit. see ?memory map? section fo r the temperature register address location. temperature register format table 1 2 -1 2 -2 2 -3 2 -4 2 -5 0 0 0 lsb msb (unit = c) lsb s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb temperature digital output (binary) digital output (hex) +125c 01111101 00000000 7d00h +25.0625c 00011001 00010000 1910h +0.5c 00000000 10000000 0080h 0c 00000000 00000000 0000h -0.5c 11111111 10000000 ff80h -25.0625c 11100110 11110000 e6f0h -55c 11001001 00000000 c900h operation-measuring battery voltage the on-board analog-to-digital convert er (adc) has 10 bits of resoluti on and will perform a conversion when the ds2438 receives a command protocol (convert v) instructing it to do so. the result of this measurement is placed in the 2-byte voltage regi ster. the range for the ds2438 adc is 0 volt to 10 volt; this range is suitable for nicd or nimh battery packs up to six cells, and for lithium ion battery packs of two cells. the full-scale range of the adc is scaled to 10.23 volt, resulting in a resolution of 10 mv. while the adc has a range that extends down to 0 volt, it is important to note that the battery voltage can also be the supply voltage to the ds2438. as such, the accuracy of the adc begins to degrade below battery voltages of 2.4 volt, and th e ability to make conversions is limited by the operating voltage range of the ds2438. voltage is expressed in this register in scaled binary format, as outlined in table 2. note that while codes exist for values below 2.4 volt, accuracy of the adc and the limitation on the ds2438?s supply voltage make it unlikely that these values would be used in actual practice. see ?memory map? section for the voltage register address location.
ds2438 5 of 29 voltage register format table 2 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 lsb msb (unit = 10 mv) lsb 0 0 0 0 0 0 2 9 2 8 msb battery voltage digital output (binary) digital output (hex) 0.05v 0000 0000 0000 0101 0005h 2.7v 0000 0001 0000 1110 010eh 3.6v 0000 0001 0110 1000 0168h 5v 0000 0001 1111 0100 01f4h 7.2v 0000 0010 1101 0000 02d0h 9.99v 0000 0011 1110 0111 03e7h 10v 0000 0011 1110 1000 03e8h for applications requiring a general purpose voltage a/d converter, the ds2438 can be configured so that the result of a convert v command will place the scaled binary representation of the voltage on the v ad input (as opposed to the v dd input) into the voltage register in th e same format described in table 2. depending upon the state of the status/configura tion register, either (but not both) the v dd or v ad voltage will be stored in the vo ltage register upon receipt of th e convert v command. refer to the description of the status/configur ation register in the memory map section for details. if the v ad input is used as the voltage input, the a/d will be accurate for 1.5v < v ad < 2v dd over the range 2.4v < v dd < 5.0v. this feature gives the user the ability to ha ve a voltage a/d that m eets spec accuracy for inputs over the entire range of 1.5v < v ad < 10v for v dd = 5.0v. operation - measuring battery current the ds2438 features an a/d converter that effectively measures the current flow into and out of the battery pack by measuring the voltage across an extern al sense resistor. it does so in the background at a rate of 36.41 measurements/sec; thus, no command is required to initiate current flow measurements. however, the ds2438 will only perform current a/d meas urements if the iad bit is set to ?1? in the status/configuration register. the ds2438 measures cu rrent flow in and out of the battery through the v sens pins; the voltage from the v sens+ pin to the v sens- pin is considered to be the voltage across the current sense resistor, r sens . the v sens+ terminal may be tied directly to the r sens resistor, however, for v sens- , we recommend use of an rc low pass f ilter between it and the gnd end of r sens (see the block diagram in figure 1). using a 100 k (min) resistor (r f ) and a 0.1 f tantalum capacitor (c f ), the filter cutoff is approximately 15.9 hz. the current a/d m easures at a rate of 36.41 times per second, or once every 27.46 ms. this filter will capture the effect of mo st current spikes, and will thus allow the current accumulators to accurately reflect the total charge which has gone into or out of the battery. the voltage across current sense resistor r sens is measured by the adc and the result is placed in the current register in two?s complement format. the sign (s) of the result, indicating charge or discharge, resides in the most significant bit of the current register, as shown in table 3. see ?memory map? in figure 7 for the current register address location.
ds2438 6 of 29 current register format table 3 (this register actually stores the voltage measured across current sense resistor r sens . this value can be used to calculate batte ry pack current using the equation below.) 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 lsb msb (unit = 0.2441mv) lsb s s s s s s 2 9 2 8 msb the battery pack current is calculated from th e current register value using the equation: i = current register / (4096 * r sens ) (where r sens is in ) for example, if 1.25a is flowing into the pack, and the pack uses a 0.025 sense resistor, the ds2438 will write the value 128 10 to the current register. from this value, battery pack current can be calculated to be: i = 128 / ( 4096 * 0.025) = 1.25a because small current adc offset errors can have a large cumulative effect when current is integrated over time, the ds2438 provides a method for canceling offs et errors in the curre nt adc. after each current measurement is completed, the measured value is added to the contents of the offset register and the result is then stored in the current register. th e offset register is a two-byte nonvolatile read/write register formatted in two?s-complement format. the f our msb?s of the register contain the sign of the offset, as shown in table 4. offset register format table 4 2 4 2 3 2 2 2 1 2 0 0 0 0 lsb msb (unit = 0.2441 mv) lsb x x x s 2 8 2 7 2 6 2 5 msb the following process can be used to calibrate the current adc: 1. write all zeroes to the offset register 2. force zero current through r sens 3. read the current register value 4. disable the current adc by setting the iad bit in the status/configuration register to ?0? 5. change the sign of the previously-read current re gister value by performing the two?s complement and write the result to the offset register 6. enable the current adc by setting the iad bit in the status/configuration register to ?1? note: when writing to the offset register, current measurement must be disabled (iad bit set to ?0?). the current adc calibration process is done for each ds2438 device prior to shipment. however, for best results, battery pack manufact urers should calibrate the curren t adc during initial battery pack testing, and the host system should calibrate whenev er possible (during battery charging, for example).
ds2438 7 of 29 operation - current accumulators the ds2438 tracks the remaining capacity of a battery using the integrated current accumulator (ica). the ica maintains a net accumulated total of current flowing into and out of the battery; therefore, the value stored in this register is an indication of the remaining capacity in a battery and may be used in performing fuel gauge functions. in addition, the ds2438 has another register that accumulates only charging (positive) current (cca) and one that accumulates only discharging (negative) current (dca). the cca and dca give the host system the information needed to determine the end of life of a rechargeable battery, based on total charge/discharge current over its lifetime. the current measurement described above yields the voltage across sense resistor r sens measured every 27.46 ms. this value is then used to increment or decrement the ica register, increment the cca (if current is positive), or increment the dca (if current is negative). the ica is a scaled 8-bit volatile binary counter that integrates the voltage across r sens over time. the ica is only incremented/decremented if the iad bit is set to 1 in the status/configuration register. table 5 illustrates the contents of the ica. see memory map se ction for the address location of the ica. ica register format table 5 (this register accumulates the voltage measured across current sense resistor r sens . this value can be used to calculate remaining battery capacity using the equation below.) 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb (unit = 0.4882 mvhr) lsb remaining battery capacity is calculated from the ica value using the equation: remaining capacity = ica / (2048 * r sens ) (where r sens is in ) for example, if a battery pack has 0.625 ahr of remaining capacity, and the pack uses a 0.025 sense resistor, the ica will contain the value 32. from this value, remaining capacity can be calculated to be: remaining capacity = 32 / ( 2048 * 0.025) = 0.625 ahr since the accuracy of the current adc is + 2 lsb, measurements of very small currents can be inaccurate by a high percentage. because these inaccuracies can turn into large ica errors when accumulated over a long period of time, the ds2438 provides a method for filte ring out potentially erroneous small signals so that they are not accumulated. the ds2438?s thres hold register specifies a current measurement magnitude (after offset cancellati on) above which the measurement is accumulated in the ica, cca and dca and below which it is not accumulated. the format of the threshold register is shown in table 6. the power-on default threshold regi ster value is 00h (no threshold). note: when writing to the threshold register, current measurement must be disabled (iad bit set to ?0?).
ds2438 8 of 29 threshold register format table 6 th2 th1 0 0 0 0 0 0 msb lsb th2 th1 threshold 0 0 none (default) 0 1 2 lsb 1 0 4 lsb 1 1 8 lsb the charging current accumulator (cca) is a two-by te nonvolatile read/write c ounter which represents the total charging current the battery has encounte red in its lifetime. it is only updated when current through r sens , is positive; i.e., when the battery is being charged. similarly, the discharge current accumulator (dca) is a two-byte nonvolatile counter which represents the total discharging current the battery has encountered over its lifetime. the cca and dca can be configured to function in an y of three modes: disabled, enabled with shadow- to-eeprom, and enabled without shadow-to-eeprom. when the cca and dca are disabled (by setting either the iad bit or the ca bit in the status/configuration register to ?0?), the memory in page 07h is free for general purpose data storage. when the cca and dca are enabled (by setting both iad and ca to ?1?), page 07h is reserved for these regi sters, and none of the bytes in page 07h should be written to via the 1-wire bus. when the cca and dca are enabled, their values are automatically shadowed to eeprom memory by setting the ee bit in the status/configuration register to ?1?. when these registers are configured to shadow to eepro m, the information will accumulate over the lifetime of the battery pack and will not be lost when the battery becomes discharged. shadow-to-eeprom is disabled when the ee bit is ?0?. table 7 illustrates the format of the cca and dca registers. table 8 summarizes the modes of opera tion for ica, cca and dca. cca/dca register format table 7 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 lsb msb (unit = 15.625 mvhr) lsb 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 msb ica/cca/dca modes of operation table 8 iad bit ca bit ee bit ica cca/dca cca/dca copy- to-eeprom 0 x x inactive inactive inactive 1 0 x active inactive inactive 1 1 0 active active inactive 1 1 1 active active active
ds2438 9 of 29 figure 2 illustrates the activity of the ica, cca, and dca over a sample charge/discharge cycle of a battery pack, assuming the ds2438 is configured for the ica to function and the cca/dca to function and shadow data to eeprom. to simplify the illustrati on of the accumulators, they are treated as analog values, although they are digital counters in th e ds2438. note that when the battery becomes fully discharged, i.e., the ica value reaches 0, the cca and dca register values are maintained. current accumulator activity figure 2 sense resistor selection the selection of r sens involves a tradeoff. on the one hand, the impedance of r sens must be minimized to avoid excessive voltage drop during peak curren t demands. on the other hand, the impedance of r sens should be maximized to achieve the finest resoluti on for current measurement and accumulation. table 9 below lists several example r sens values, the lsb of the current calculation ( 1/(4096 * r sens ) ) and the lsb of the remaining capacity calculation ( 1/(2048 * r sens ) ). the user should carefully consider voltage drop at maximum current and required cu rrent measurement/accumulation resolution when selecting r sens . sense resistor tradeoffs table 9 sense resistor value (r sens ) current lsb remaining capacity lsb max remaining capacity value 25 m 9.76 ma 19.53 mahr 5000 mahr 50 m 4.88 ma 9.76 mahr 2500 mahr 100 m 2.44 ma 4.88 mahr 1250 mahr 200 m 1.22 ma 2.44 mahr 625 mahr operation - elapsed time meter an internal oscillator is used as the timebase for the timekeeping functions. the elapsed time functions are double buffered, allowing the master to read elap sed time without the data changing while it is being read. to accomplish this, a snapshot of the counter data is transferred to holding registers which the user accesses. this occurs after the 8t h bit of the recall memory command. the elapsed time meter (etm) is a 4-byte binary counter with 1-second resolution. the etm can accumulate 136 years of seconds before rolling over. t ime/date is represented by the number of seconds since a reference point, which is determined by th e user. for example, 12:00 a.m., january 1, 1970 could be used as a reference point.
ds2438 10 of 29 two other time-related functions are available. the first is the disconn ect timestamp, which is written to by the ds2438 whenever it senses that the dq line has been low for approximately 2 seconds. this condition would signal that the battery pack has been removed from the system; the time when that occurs is written into the disconnect timestamp regi ster, so that upon replacement into the system, the system can determine how long the device has been in storage, to facilitate self-discharge corrections to the remaining battery capacity. after the disconnect has been detected, the ds2438 reverts to a sleep mode, during which nothing is active except the real time clock. some applications may prefer that the data converters and current accu mulators continue operation following a pack disconnect. thus, a version of the ds2438 (part number ds 2438a) is offered for those applica tions. other than not reverting to a low-power sleep mode following disconnect, there are no specification differences between the ds2438 and the ds2438a. the other timestamp is the end-of-charge timestamp, which is written to by the ds2438 whenever it senses that charging is finished (when current changes direction). this timestamp allows the user to calculate the amount of time the battery has been in a discharge or storage state, again to facilitate self- discharge calculations. the format of the etm, disconnect, and end-of-charge registers are as shown in table 10. refer to the ?memory map? section for the address location of the time-related registers. time register format table 10 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 lsb msb (unit = 1s) lsb 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 msb (unit = 1s) lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 msb (unit = 1s) lsb 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 msb 64-bit lasered rom each ds2438 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code (ds2438 code is 26h). the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (see figure 3.) the 64-bit rom and rom f unction control section allow the ds2438 to operate as a 1-wire device and follow the 1-wire protocol detailed in the section ?1-wire bus system.? the functions required to control sections of the ds24 38 are not accessible until the rom function protocol has been satisfied. this protocol is described in the rom function pr otocol flow chart (figure 5). the 1-wire bus master must first pr ovide one of four rom function co mmands: 1) read rom, 2) match rom, 3) search rom, or 4) skip rom. after a rom function sequence has been successfully executed, the functions specific to the ds2438 are accessible and the bus master may then provide any one of the six memory and control function commands.
ds2438 11 of 29 64-bit lasered rom format figure 3 8-bit crc code 48-bit serial number 8-bit family code (26h) msb lsb msb lsb msb lsb crc generation the ds2438 has an 8-bit crc stored in the most signif icant byte of the 64-bit rom. the bus master can compute a crc value from the first 56 bits of the 64-bit rom and compare it to the value stored within the ds2438 to determine if the rom da ta has been received error-free by the bus master. the equivalent polynomial function of this crc is: crc = x 8 + x 5 + x 4 +1 the ds2438 also generates an 8-bit crc value usin g the same polynomial f unction shown above and provides this value to the bus master to validate the transfer of data bytes. in each case where a crc is used for data transfer validation, the bus master must calculate a crc value using the polynomial function given above and compare the calculated value to either the 8-bit crc value stored in the 64-bit rom portion of the ds2438 (for rom reads) or th e 8-bit crc value computed within the ds2438 (which is read as a 9th byte when a scratchpad is read). the comparison of crc values and decision to continue with an operation are determined entirely by the bus master. there is no circuitry inside the ds2438 that prevents a command sequence from proceedin g if the crc stored in or calculated by the ds2438 does not match the value generated by the bus master. proper use of the crc as outlined in the flowchart of figure 6 can result in a communicati on channel with a very high level of integrity. the 1-wire crc can be generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. additional information about the dallas 1-wire cy clic redundancy check is available in application note 27 entitled ?understanding and usin g cyclic redundancy checks with dallas semiconductor touc h memory products.? the shift register bits are initialized to 0. then star ting with the least significant bit of the family code, 1 bit at a time is shifted in. after the 8 th bit of the family code has been entered, the serial number is entered. after the 48 th bit of the serial number has been ente red, the shift register contains the crc value. 1-wire crc code figure 4
ds2438 12 of 29 rom functions flowchart figure 5
ds2438 13 of 29 memory/control functions flowchart figure 6 yes no
ds2438 14 of 29 memory/control functions flowchart figure 6 (continued) memory map the ds2438?s memory is organized as shown in figu re 7. the memory consists of a scratchpad ram and storage sram/eeprom. the scratchpad helps insure data integrity when communicating over the 1-wire bus. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command will transfer the data to the appropriate page in memory (pages 0-2 are primarily volatile sram, pages 3-7 are eeprom). this process insures data integrity when modifying the memory. the ds2438?s memory is organized as 64 bytes of memory , in eight 8-byte pages. each page has its own scratchpad space, organized as 8 bytes of memory. when reading a scratchpad, there is a 9th byte which may be read with a read scratchpad command. this byte contains a cyclic redundancy check (crc) byte, which is the crc over all of the 8 bytes in the currently selected scratchpad. this crc is implemented in the fashion described in the section titled ?crc generation.?
ds2438 15 of 29 page 0 (00h) the first page contains the most frequently accessed information of the ds2438, and most locations are volatile read-only bytes with the exception of the status/configuration register (byte 0) and the threshold register (byte 7). the status/configurati on register is a nonvolatile read/write byte which defines which features of the ds2438 are enabled and how they will function. the register is formatted as follows: x adb nvb tb ad ee ca iad msb lsb iad = current a/d control bit. ?1? = the current a/d and the ica are enabled, and current measurements will be taken at the rate of 36.41 hz; ?0? = the current a/d and the ica have been disabled. the default value of this bit is a ?1? (current a/d and ica are enabled). ca = current accumulator configuration. ?1? = cca/dca is enabled, and data will be stored and can be retrieved from page 7, bytes 4-7; ?0? = cca/dca is disabled, and page 7 can be used for general eeprom storage. the default value of this bit is a ?1? (current cca/dca are enabled). ee = current accumulator shadow selector bit. ?1? = cca/dca counter data will be shadowed to eeprom each time the respective register is increm ented; ?0?= cca/dca c ounter data will not be shadowed to eeprom. the cca/dca could be lost as the battery pack becomes discharged. if the ca bit in the status/configuration re gister is set to ?0?, the ee bit will have no effect on the ds2438 functionality. the default value of this bit is a ?1? (current cca/dca data shadowed to eeprom). ad = voltage a/d input select bit. ?1? = the battery input (vdd) is selected as the input for the ds2438 voltage a/d converter; ?0? = the general purpos e a/d input (vad) is se lected as the voltage a/d input. for either setting, a convert v command will initialize a voltage a/ d conversion. the default value of this bit is a ?1? (v dd is the input to the a/d converter). tb = temperature busy flag. ?1? = temperature convers ion in progress; ?0? = temperature conversion complete. nvb = nonvolatile memory busy flag. ?1? = copy fro m scratchpad to eeprom in progress; ?0? = nonvolatile memory not busy. a copy to eeprom may take from 2 ms to 10 ms (taking longer at lower supply voltages). adb = a/d converter busy flag. ?1? = a/d conversion in progress on battery voltage; ?0? = conversion complete, or no measurement being made. an a/d conversion takes approximately 10 ms. x = don?t care bytes 1 and 2 of page 0 contain the last completed temperature conversion in the format described in the ?operation - measuring temperature? section. by tes 3-4 contain the last completed voltage a/d conversion result and bytes 5-6 contain the instantane ous current data. byte 7 contains the threshold register. refer to the appr opriate section for the data format of these locations. note: the data in the scratchpad of the status and threshold register will determine the operation of the device.
ds2438 16 of 29 page 1 (01h) the second page, page 1, contains the ica, elasped time meter, and current offset data. both the etm and ica are volatile read/write locations so that they may be set, changed, or cleared by the host software. bytes 0-3 contain the etm data, formatted as described in the ?operation - elapsed time meter? section. byte 4 contains the 8- bit ica. bytes 5 and 6 contain the offset register data. byte 7 is reserved and will read out as all ?1?s. page 2 (02h) the third page of memory (page 2) contains the disc onnect (first 4 bytes) and end of charge (remaining 4 bytes) timestamps. this page is volatile and read/write. refer to the ?operation ? elapsed time meter? section for the formatting of these locations. pages 3-7 (03h - 07h) the remainder of the memory in the ds2438 (pages 3 through 7) is backed with eeprom. this memory provides 40 bytes of user memory which may be used to carry any information the user wishes to store. additionally, the cca/dca information is stored in bytes 4-7 of page 7 if the ds2438 is configured appropriately. if the cca/dca is used, page 7 should not be written to or current accumulator data will be overwritten. see ?operation-current accumulators? for details. memory map figure 7 page byte contents r/w nv page byte contents r/w nv 0 status/ configuration r/w yes 0 user byte r/w yes 1 temperature lsb r no 1 user byte r/w yes 2 temperature msb r no 2 user byte r/w yes 0 3 voltage lsb r no 3 3 user byte r/w yes 4 voltage msb r no 4 user byte r/w yes 5 current lsb r no 5 user byte r/w yes 6 current msb r no 6 user byte r/w yes 7 threshold r/w yes 7 user byte r/w yes 0 etm byte 0 r/w no 0 user byte r/w yes 1 etm byte 1 r/w no 1 user byte r/w yes 2 etm byte 2 r/w no 2 user byte r/w yes 1 3 etm byte 3 r/w no 3 user byte r/w yes 4 ica r/w no 4 4 user byte r/w yes 5 offset lsb r/w yes 5 user byte r/w yes 6 offset msb r/w yes 6 user byte r/w yes 7 reserved 7 user byte r/w yes r/w no 0 disconnect byte 0 r/w no 1 disconnect byte 1 r/w no 2 disconnect byte 2 r/w no 2 3 disconnect byte 3 r/w no 0 user byte r/w yes 4 end of charge byte 0 r/w no 1 user byte r/w yes 5 end of charge byte 1 r/w no 2 user byte r/w yes 6 end of charge byte 2 r/w no 7 3 user byte r/w yes 7 end of charge byte 3 r/w no 4 user byte/ cca lsb r/w yes 5 user byte/ cca msb r/w yes 6 user byte/ dca lsb r/w yes 7 user byte/ dca msb r/w yes
ds2438 17 of 29 1-wire bus system the 1-wire bus is a system which has a single bus master and one or more slaves. the ds2438 behaves as a slave. the discussion of this bus system is broken down into three topics : hardware configuration, transaction sequence, and 1-wire signaling (signal types and timing). hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to f acilitate this, each device attached to the 1-wire bus must have open drain or 3-state outputs. the 1-wire port of the ds2438 (dq pin) is open drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the 1-wire bus requires a pu ll-up resistor of approximately 5 k . hardware configuration figure 8 the idle state for the 1 wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. infinite recovery time can occur between bits so long as the 1-wire bus is in the inactive (h igh) state during the recovery period. if this does not occur and the bus is left low, all components on the bus will be reset. see wire-1 reset pulse timing (figure 9). transaction sequence the protocol for accessing the ds2438 via the 1-wire port is as follows: initialization rom function command memory function command transaction/data initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds2438 is on the bus and is ready to operate. for more details, see the ?1-wire signaling? section.
ds2438 18 of 29 rom function commands once the bus master has detected a presence, it can issue one of the four rom function commands. all rom function commands are 8-bits long. a list of these commands follows (refer to flowchart in figure 5): read rom [33h] this command allows the bus master to read the ds2438?s 8-bit family code ( 26h), unique 48-bit serial number, and 8-bit crc. this command can only be used if there is a single ds2438 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open-drain will produce a wired-and result). match rom [55h] the match rom command, followed by a 64-bit rom se quence, allows the bus master to address a specific ds2438 on a multidrop bus. only the ds2438 th at exactly matches the 64-bit rom sequence will respond to the following memory function comma nd. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing th e 64-bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simulta neously (open drain pull-downs will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus mast er might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search ro m command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus. example of a rom search the rom search process is the repetition of a simple three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, three-step routine on each bit of the rom. after one complete pass, th e bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. the following example of the rom search process assumes four different devices are connected to the same 1-wire bus. the rom data of the f our devices is as shown (lsb first): rom1 = 00110101... rom2 = 10101010... rom3 = 11110101... rom4 = 00010001... the search process is as follows: 1. the bus master begins the initialization sequence by issuing a reset pulse. the slave devices respond by issuing simultaneous presence pulses. 2. the bus master will then issue the search rom command on the 1-wire bus (f0h).
ds2438 19 of 29 3. the bus master reads a bit from the 1-wire bus. e ach device will respond by placing the value of the first bit of their respective rom data onto the 1-wire bus. rom1 and rom4 will place a 0 onto the 1-wire bus, i.e., pull it low. rom2 and rom3 will place a 1 onto the 1-wire bus by allowing the line to stay high. the result is the logical and of all devices on the line; therefore the bus master sees a 0. the bus master reads another bit. since the search rom data command is being executed, all of the devices on the 1-wire bus respond to this second read by placing the complement of the first bit of their respective rom data onto the 1-wire bus. rom1 and rom4 will place a 1 onto the 1-wire, allowing the line to stay high. rom2 and rom3 w ill place a 0 onto the 1-wire, thus it will be pulled low. the bus master again observes a 0 for the complement of the first rom data bit. the bus master has determined that there are some devices on the 1-wire bus that have a 0 in the first position and others that have a 1. the data obtained from the two reads of the three-step routine have the following interpretations: 00 - there are still devices attached which have conflicting bits in this position. 01 - all devices still coupled have a 0 bit in this bit position. 10 - all devices still coupled have a 1 bit in this bit position. 11 - there are no devices attached to the 1-wire bus. 4. the bus master writes a 0. this deselects rom2 a nd rom3 for the remainder of this search pass, leaving only rom1 and rom4 connected to the 1-wire bus. 5. the bus master performs two more reads and receives a 0 bit followed by a 1 bit. this indicates that all devices still coupled to the bus have 0s as their second rom data bit. 6. the bus master then writes a 0 to keep both rom1 and rom4 coupled. 7. the bus master executes two reads and receives two 0 bits. this indicates that both 1 bits and 0 bits exist as the 3rd bit of the rom data of the attached devices. 8. the bus master writes a 0 bit. this deselects ro m1, leaving rom4 as the only device still connected. 9. the bus master reads the remainder of the rom b its for rom4 and continues to access the part if desired. this completes the first pass and uni quely identifies one pa rt on the 1-wire bus. 10. the bus master starts a new rom search sequence by repeating steps 1 through 7. 11. the bus master writes a 1 bit. this dec ouples rom4, leaving only rom1 still coupled. 12. the bus master reads the remainder of the rom bits for rom1 and communicates to the underlying logic if desired. this completes the second rom search pass, in which another of the roms was found. 13. the bus master starts a new rom search by repeating steps 1 through 3. 14. the bus master writes a 1 bit. this deselects rom1 and rom4 for the remainder of this search pass, leaving only rom2 and rom3 coupled to the system. 15. the bus master executes two read time slots and receives two 0s.
ds2438 20 of 29 16. the bus master writes a 0 bit. this d ecouples rom3, and leaving only rom2. 17. the bus master reads the remainder of the rom bits for rom2 and communicates to the underlying logic if desired. this completes the third rom sear ch pass, in which another of the roms was found. 18. the bus master starts a new rom search by repeating steps 13 through 15. 19. the bus master writes a 1 bit. this decouples rom2, leaving only rom3. 20. the bus master reads the remainder of the rom bits for rom3 and communicates to the underlying logic if desired. this completes the fourth rom search pass, in which another of the roms was found. note that the bus master learns the unique id number (rom data pattern) of one 1-wire device on each rom search operation. the time required to derive the part?s unique rom code is: 960 s + (8 + 3 x 64) 61 s = 13.16 ms the bus master is therefore capable of iden tifying 75 different 1-wire devices per second. memory command functions the following command protocols are summarized in table 11, and by the flowchart of figure 6. write scratchpad [4ehxxh] this command writes to the scratchpad page xxh of the ds2438. the entire 8-byte scratchpad space may be written, but all writing begins with the byte present at address 0 of the selected scratchpad. after issuing this command, the user must send the page numbe r of the scratchpad to be written; then the user may begin writing data to the ds2438 scratchpad. writing may be terminated at any point by issuing a reset. valid page numbers for writing are 00h-07h. read scratchpad [behxxh] this command reads the contents of the scratchpad page xxh on the ds2438. after issuing this command, the user must send the page number of the scratchpad to be read, and then may begin reading the data, always beginning at address 0 of the selected scra tchpad. the user may read through the end of the scratchpad space (byte 07h), with any reserved data bits reading all logic 1s, then read the crc of the data, and after which the data read will be all logic 1s. if not all locations are to be read, the master may issue a reset to terminate reading at any time. valid page numbers are 00h - 07h. copy scratchpad [48hxxh] this command copies the scratchpad page xxh into the eeprom / sram memory page xxh of the ds2438. after issuing this command, the user must write a page number to direct which page of memory the scratchpad is to be copied. valid page numbers are 00h - 07h. during the copy function, the nvb bit in the status/configuration register will be set to a ?l?. when the copy is complete, this bit will reset to ?0?. if the bus master issues read time slots following this command, the ds2438 will output ?0? on the bus as long as it is busy copying the scratchpad to sram/eeprom; it will return a ?1? when the copy process is complete.
ds2438 21 of 29 recall memory [b8hxxh] this command recalls the stored values in eeprom / sram page xxh to the scratchpad page xxh. this command must proceed a read spxx command in orde r to read any page of memory on the ds2438. valid page numbers are 00h - 07h. convert t [44h] this command begins a temperature conversion. no furt her data is required. the temperature conversion will be performed, setting the tb flag in the status /configuration register to a ?1? during conversion. when the temperature conversion is done, the tb flag w ill clear to a ?0?. if the bus master issues read time slots following this command, the ds2438 will output ?0? on the bus as long as it is busy making a temperature conversion; it will return a ?1? wh en the temperature conversion is complete. convert v [b4h] this command instructs the ds2438 to initiate a voltage analog-to-digital conversi on cycle. this sets the adb flag (see status/configuration register discussi on in the memory map section). the voltage supply that is measured is defined by the ad bit of the st atus/configuration register. when the a/d conversion is done, the adb flag is cleared and the current vo ltage value is placed in the voltage register of page 00h. while an a/d conversion is taking place, all other memory func tions are still available for use. if the bus master issues read time slots following this command, the ds2438 will output ?0? on the bus as long as it is busy making a voltage measurement; it will return a ?1? when the conversion is complete. ds2438 command set table 11 instruction description protocol 1-wire bus master status after issuing protocol 1-wire bus data after issuing protocol memory commands read scratchpad reads bytes from ds2438 scratchpad page xxh beh rx write scratchpad writes bytes to ds2438 scratchpad page xxh 4eh tx copy scratchpad copies entire contents of scratchpad page xxh to 8-byte eeprom/ sram page xxh 48h idle or rx of nvb bit {nvb bit in status register = 1 until copy complete (2- 10 ms, typ)} recall memory copies entire contents of eeprom/sram page xxh to scratchpad page xxh b8h idle idle register commands convert t initiates temperature conversion 44h idle or rx of tb bit {tb bit in status register = 1 until conversion complete} convert v initiates voltage a/d conversion b4h idle or rx of adb bit {adb bit in status register = 1 until conversion complete}
ds2438 22 of 29 notes: 1. temperature conversion takes up to 10 ms. 2. a/d conversion takes up to 4 ms. 3. eeprom writes take up to 10 ms. sample command sequence table 12 example: bus master enables the ica, cca, and dc a on a single ds2438 and configures it such that the cca/dca information is shadowed to eeprom. the voltage a/d is configured such that the ds2438 will perform voltage measuremen ts on the battery (vdd) voltage. master mode data (lsb first) comments tx reset read pulse rx presence presence pulse tx cch skip rom tx 4eh00h issue write sp 00h command tx 0fh sets ica, ca, ee, ad bits active tx reset re set pulse rx presence presence pulse tx cch skip rom tx beh00h issue read sp 00h command rx <9 data bytes> read scratchpad data and crc tx reset re set pulse rx presence presence pulse tx cch skip rom tx 48h00h issue copy sp 00h command rx read slots ds2438 returns a ?1 ? when copy sp is complete tx reset re set pulse rx presence presence pulse, done
ds2438 23 of 29 sample command sequence table 13 example: bus master issues a temperature and volta ge conversion, then reads the temperature, battery voltage, battery current, all on a single ds2438. master mode data (lsb first) comments tx reset re set pulse rx presence presence pulse tx cch skip rom tx 44h issue convert temperature command, read slots tx reset re set pulse rx presence presence pulse tx cch skip rom tx b4h issue convert voltage command, read slots tx reset re set pulse rx presence presence pulse tx cch skip rom tx b8h00h issue recall memory page 00h command tx reset re set pulse rx presence presence pulse tx cch skip rom tx beh00h issue read sp 00h command rx <9 data bytes> read scratchpad data and crc. this page contains temperature, voltage, and current measurements. tx reset re set pulse rx presence presence pulse, done
ds2438 24 of 29 sample command sequence table 14 example: assuming a single ds2438 is configured for its current accumulators to function, this sequence allows the bus master to read the three current accumulators. master mode data (lsb first) comments tx reset re set pulse rx presence presence pulse tx cch skip rom tx b8h01h issue recall memory page 01h command tx reset re set pulse rx presence presence pulse tx cch skip rom tx beh01h issue read sp 01h command rx <9 data bytes> read scratchpad data and crc. the ica is located in byte 04h tx reset re set pulse rx presence presence pulse tx cch skip rom tx b8h07h issue recall memory page 07h command tx reset re set pulse rx presence presence pulse tx cch skip rom tx b8h07h issue read sp 07h command rx <9 data bytes> read scratchpad data and crc. the cca is located in bytes 04h-05h and the dca is located in bytes 06h-07h. tx reset re set pulse rx presence presence pulse, done i/o signaling the ds2438 requires strict protocols to insure data integrity. the protoc ol consists of several types of signaling on one line: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. all of these signals, with the exception of the presence pulse, are initiated by the bus master. the initialization sequence required to begin any co mmunication with the ds2438 is shown in figure 9. a reset pulse followed by a presence pulse indicates the ds2438 is ready to send or receive data given the correct rom command and memory function command. th e bus master transmits (tx) a reset pulse (a low signal for a minimum of 480 s). the bus master then releases the line and goes into a receive mode(rx). the 1-wire bus is pu lled to a high state via the 5 k pull-up resistor. after detecting the rising edge on the i/o pin, the ds2438 waits 15-60 s and then transmits the presence pulse (a low signal for 60-240 s). ds2438 data is read and written through the use of time sl ots to manipulate bits and a command word to specify the transaction.
ds2438 25 of 29 initialization procedure ?reset and presence pulses? figure 9 480 s t rstl < * 480 s t rsth < (includes recovery time) 15 s t pdh < 60 s 60 s t pdl < 240 s write time slots a write time slot is initiated when the host pulls the data line from a high (inactive) logic level to a low logic level. there are two types of write time slots: write 1 time slots and write 0 time slots. all write time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between individual write cycles. the ds2438 samples the i/o line in a window of 15 s to 60 s after the i/o line falls. if the line is high, a write 1 occurs. if the line is low, a write 0 occurs (see figure 10). for the host to generate a write 1 time slot, the data line must be pulled to a logic low level and then released, allowing the data line to pull up to a high level within 15 microseconds after the start of the write time slot. for the host to generate a write 0 time slot, the data line must be pulled to a logic low level and remain low for the dur ation of the write time slot. read time slots the host generates read time slots when data is to be read from the ds2438. a read time slot is initiated when the host pulls the data line from a logic high level to logic low level. the data line must remain at a low logic level for a minimum of 1 s; output data from the ds2438 is then valid within the next 14 s maximum. the host therefore must stop driving the i/o pin low in order to read its state 15 s from the start of the read slot. (see figure 10). by the end of the read time slot, the i/o pin will pull back high via the external pull-up resistor. all read time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between individual read slots. resistor master ds2438
ds2438 26 of 29 read / write timing diagram figure 10 write-one time slot ds2438 sampling window 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < write-zero time slot ds2438 60 s t low0 < t slot < 120 s 1 s t rec < read-data time slot 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s resistor master resistor master ds2438
ds2438 27 of 29 absolute maximum ratings* voltage on vdd and vad, relative to ground -0.3v to + 12v voltage on vsens+, vsens-, re lative to ground <300 mv voltage on any other pin relativ e to ground -0.3v to + 7.0v operating temperature -40c to +85c storage temperature -55c to +125c soldering temperature see j-std-020a specification * this is a stress rating only and f unctional operation of the device at these or any other conditions above those indicated in the operation s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (-40 c to +85 c; 2.4v vdd 10.0v) parameter symbol condition min typ max units notes supply voltage v dd 2.4 10.0 v 1 data pin dq -0.3 +5.5 v 1 dq pull-up voltage 2.4 5.5 dc electrical characteristics (-40 c to +85 c; 2.4v vdd 10.0v) parameter symbol condition min typ max units notes input logic high v ih 2.0 v 1 input logic low v il -0.3 0.5 v 1 shutdown current i dd1 dq=0, rtc active 25 a active current i dd dq=1, ica active or temperature or voltage conversions or eeprom write in progress 50 100 a input resistance r i dq 500 k 2
ds2438 28 of 29 electrical characteristic s: digital thermometer (-40 c to +85 c; 2.4v vdd 10.0v) parameter symbol condition min typ max units notes thermometer error (t actual - t measured ) t err 2 c conversion time t convt 3 10 ms electrical characteristic s: voltage a/d converter (-40 c to +85 c; 2.4v vdd 10.0v) parameter symbol condition min typ max units notes a/d error vdd err vad err vdd input vad input 10 25 50 75 mv v ad input range v adr 1.5v 10.0 v 1 v dd input range v ddr 2.4 10.0 v 1 conversion time t convv 3 10 ms no missing code temperature range -40 +85 c electrical characteristics: current a/d converter (-40 c to +85 c; 2.4v vdd 10.0v) parameter symbol condition min typ max uni ts notes current measurement input range (v sens+ - v sens- ) iad range 250 mv current measurement error iad err |v sens+ - v sens- | 125 mv 2 1 lsb % 3 electrical characteristics: rtc counter (-40 c to +85 c; 2.4v vdd 10.0v) parameter symbol condition min typ max units notes clock error rtc err 0c to +70c 1 3 % resolution 1 sec
ds2438 29 of 29 ac electrical characteristics: nv memory (-40 c to +85 c; 2.4v vdd 10.0v) parameter symbol condition min typ max units notes nv write cycle time t wr 2 10 ms eeprom writes (copy scratchpad command) n eewr -20oc to +55oc 50k writes eeprom data retention t eedr -20oc to +55oc 10 years ac electrical characteristics: 1-wire interface (-40 c to +85 c; 2.4v vdd 10.0v) parameter symbol condition min typ max units notes time slot t slot 60 120 s recovery time t rec 1 s write 0 low time t low0 60 120 s write 1 low time t low1 1 15 s read data valid t rdv 15 s reset time high t rsth 480 s reset time low t rstl 480 980 s presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s dq capacitance c dq 25 pf notes: 1. all voltages are referenced to gnd. 2. input load is to gnd. 3. current measurement accuracy is 2 lsb or 1%, whichever is greater.

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